1. Field of the Invention
The present invention relates to a memory device, and more particularly to a non-volatile single-poly memory device, which is capable of providing improved data correctness. The present invention non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.
2. Description of the Prior Art
Non-volatile memory is one of the major data storage devices today. The most important feature is that non-volatile memory can retain the stored information even when not powered. Generally speaking, memory devices such as hard drives, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory are non-volatile memory devices, because all information is still available in the absence of power supply.
As the demand for small size portable electrical devices such as personal digital assistants or cellular phones increases, there is a great need of the embedded chips for logic circuits and system on a chip. A flash memory, which is process compatible with CMOS logic processes and has low power consumption, high writing efficiency, low cost and high packing density, will meet the market demands.
FIG. 1 is a schematic layout of a non-volatile memory cell according to U.S. Pat. No. 6,678,190. As shown in FIG. 1, memory cell 1 includes two serially connected PMOS transistors 12 and 14, wherein the PMOS transistor 12 includes a select gate 4, a P+ drain/source doped region 8, and a P+ drain/source doped region 2, and the PMOS transistor 14 includes a floating gate 6, a P+ drain/source doped region 9, and the P+ drain/source doped region 2. The PMOS transistors 12 and 14 share the P+ drain/source doped region 2 mutually.
During operation, the select gate 4 of the PMOS transistor 12 is coupled to a select gate voltage VSG, the P+ drain/source doped region 8 of the PMOS transistor 12 is coupled to a source line voltage VSL through a contact plug 22, the P+ drain/source doped region 2 and the floating gate 6 are floating. The P+ drain/source doped region 9 of the PMOS transistor 14 is coupled to a bit line voltage VBL through a contact plug 24. During writing operation, electrons are selectively injected and stored in the floating gate 6.
The advantage of the abovementioned memory structure is that it can be operated under low voltages, and both of the PMOS transistors 12 and 14 are composed of a single layer of polysilicon such that they are fully compatible with logic processes.
However, in some situations where higher data correctness is required, for example, no data error is permitted so that the aforesaid memory cell may not be able to achieve customer's strict requirements. In other cases, when the flexibility of semiconductor processes is not adequate which might affect the charge retention ability of the non-volatile memory device, a few bits within the memory array may have charge retention problem, so new ideas are needed to improve the process flexibility.
Therefore, there is a strong need in this industry to provide a non-volatile single-poly memory device, which is capable of improving data correctness and operating at low voltages, and is fully compatible with logic processes.